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| Ordering number : EN*4852B CMOS LSI LC89512W CD-ROM Error Correction LSI with Built-In SCSI Interface Preliminary Overview The LC89512W integrates a real-time error correction circuit and a SCSI interface in a single chip. Package Dimensions unit: mm 3181A-SQFP100 [LC89512W] Functions * CD-ROM error correction function, subcode readout function, SCSI interface Features * Support for double-speed drives at an operating frequency of 16.9344 MHz Either SRAM (120 ns), DRAM (80 ns) or pseudo SRAM (85 ns) can be used. * Support for quad-speed drives at an operating frequency of 33.8688 MHz SRAM (70 ns) must be used. * Built-in SCSI interface with built-in 48 mA sink buffer (Only the TARGET function is supported.) * Built-in 12-byte output FIFO for sub-CPU to host computer data transmission * Built-in 12-byte input FIFO for host computer to subCPU data transmission * Subcode data can be written to buffer RAM and the subCPU can read the subcode values by connecting the LC89512 to the CD-DSP subcode pin. * Sub-CPU access of buffer RAM through the LC89512 * Built-in function for buffer RAM internal data transfer * Pseudo-SRAM (128-kword x 8-bit and smaller) can be used. * DRAM (two 256-kword x 4-bit chips or two 1-Mword x 4-bit chips) can be used. * Transfer speeds: 2.8 MB/second (asynchronous mode) (for CD-ROM decode only operation) 4.2 MB/second (synchronous mode) (CD-ROM decode operation is not supported in synchronous mode) Both of these transfer modes use a 16.9344 MHz clock. (The transfer speed depends on the frequency used.) * Operating frequencies: 16.9344 MHz (up to double speed), 33.8688 (quad speed) SANYO: SQFP100 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN O3095HA (OT)/D1694TH (OT) No. 4852-1/5 LC89512W Block Diagram No. 4852-2/5 LC89512W Pin Functions Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Pin DB7 VSS1 DBP ATN VSS1 BSY ACK VSS1 RST MSG VSS1 SEL C/D VSS1 REQ I/O VSS0 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 INT1 VSS0 VSS0 D0 D1 D2 D3 D4 D5 D6 D7 INT0 XTALCK XTAL VSS0 VDD RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 Type B P B B P B B P B B P B B P B B P B B B B B B B B O P P B B B B B B B B O I O P P O O O O O O O O O O O O Data buffer RAM address signal outputs Microprocessor interrupt request signal output Crystal oscillator circuit input Crystal oscillator circuit output Microprocessor data signals These pins have built-in pull-up resistors. SCSI block interrupt request signal output (set using a register) Data buffer RAM data signals These pins have built-in pull-up resistors. SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection Function Continued on next page. No. 4852-3/5 LC89512W Continued from preceding page. Pin No. 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VDD VSS1 DB0 DB1 VSS1 DB2 DB3 VSS1 DB4 DB5 VSS1 DB6 Pin RA12 RA13 RA14 RA15 RA16 RA17 VDD VSS0 RESET TEST1 TEST2 TEST3 WFCK SBSO SCOR SDATA BCK LRCK C2PO RD WR CS RS VSS0 SWAIT EXCK MCK TEST0 RCS RWE ROE Type O O O O O O P P I I I I I I I I I I I I I I I P O O O I O O O NC NC NC NC P P B B P B B P B B P B SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection Sub-CPU wait signal Sub code I/O Crystal oscillator frequency output Test inputs. These pins should be tied low in normal operation . RAM chip select RAM data write signal output RAM data read signal output Serial data input Serial data input clock 44.1 kHz strobe signal input C2 pointer input Microprocessor data read signal input Microprocessor data write signal input Chip select signal input (from the microprocessor) Register selection signal input Subcode I/O Test inputs. These pins should be tied low in normal operation. Reset Data buffer RAM address signal outputs Function Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Note: 1. NC must be left open. Do not connect any signals to these pins. 2. VSS0 is the logic system ground and VSS1 is the SCSI interface ground. (from the standard cell version) Continued on next page. No. 4852-4/5 LC89512W Specifications Absolute Maximum Ratings at VSS = 0 V Parameter Maximum supply voltage I/O voltages Allowable power dissipation Operating temperature Storage temperature Soldering thermal stress limit (pins only) Symbol VDD max VI VO Pd max Topr Tstg 10 seconds Ta = 25C Ta = 25C Ta 70C Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 350 -30 to +70 -55 to +125 260 Unit V V mW C C C Allowable Operating Ranges at Ta = -30 to +70C, VSS = 0 V Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions min 4.5 0 typ 5.0 max 5.5 VDD Unit V V DC Characteristics at Ta = -30 to +70C, VSS = 0 V, VDD = 4.5 to 5.5 V Parameter Input high level voltage Input low level voltage Input high level voltage Input low level voltage Input high level voltage Input low level voltage Output high level voltage Output low level voltage Output low level voltage Output low level voltage Input leakage current Pull-up resistance Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOL2 VOL3 IL RUP Conditions All input pins other than (1), (3), and XTALCK RESET, IO0 to IO7, D0 to D7, RD, CS, WR, WFCK, SBSO and SCOR(1) ACK, ATN and the input pins (3) IOH1 = -3 mA: IO0 to IO7, D0 to D7 and all output pins other than (2), (3) and XTALCK IOL1 = 3 mA: IO0 to IO7, D0 to D7 and all output pins other than (2), (3) and XTALCK IOL2 = 3 mA: INT1 and INT0 (pull-up resistor open drain) (2) IOL3 = 48 mA: DB0 to DB7, DBP, BSY, I/O, MSG, SEL, RST, REQ, C/D (2) VI = VSS, VDD: All input pins IO0 to IO7, D0 to D7, INT1 and INT0 -25 40 80 min 2.2 0.8 2.5 0.6 2.0 0.8 2.4 0.4 0.4 0.4 +25 160 typ max Unit V V V V V V V V V V A k s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 4852-5/5 |
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